"At the material level, InGaAs is InGaAs. The physics advantage over silicon in SWIR does not change whether it is grown on InP or silicon. The question isn't whether it functions (it clearly does), but whether performance, defect density, dark current, and reliability meet target specs while achieving manufacturable yields on 200–300mm silicon."
So lets remove the substrate out of the equation. How does Aeluma create an equal or better InGaAs SWIR sensor than all the other big companies also making InGaAs SWIR sensors?
Thank you for the thoughtful question — it cuts straight to the heart of the issue.
You’re correct: InGaAs is InGaAs. The fundamental SWIR absorption physics do not change whether it’s grown on InP or silicon. Established InGaAs-on-InP suppliers have excellent devices today with strong QE, low dark current, and long qualification history.
The differentiation is not material physics — it is manufacturing architecture.
Traditional InP wafers are small-diameter (often 2–4 inches), higher-cost substrates that limit die count per wafer and constrain scaling into cost-sensitive, high-volume markets.
Aeluma’s approach integrates InGaAs onto large-diameter (200–300mm) silicon wafers using CMOS-aligned processing. The implications are structural:
• materially higher die count per wafer
• potential for significantly lower cost per unit at scale
• better alignment with automated silicon manufacturing flows
• tighter integration with CMOS electronics and photonics
Publicly disclosed data suggests competitive QE and dark current metrics within targeted regimes, including elevated-temperature testing relevant to automotive and defense environments. The remaining proof point is sustained yield, reliability, and qualification at wafer scale.
So the comparison is not “InGaAs vs InGaAs.”
It is “InGaAs on small InP wafers” versus “InGaAs on large silicon wafers integrated into silicon infrastructure.”
If Aeluma can maintain performance while achieving silicon-scale economics, differentiation emerges at the cost and integration level — not the raw material level.
That is the crux of the moat question — and why execution at scale could create meaningful economic differentiation.
Happy to discuss specific competitors or qualification timelines further if helpful.
wow a substack dedicated to a single stock props man
I write where I have differentiated work to share. Always open to new ideas and to debating the substance.
From your comment on Seekingalpha:
"At the material level, InGaAs is InGaAs. The physics advantage over silicon in SWIR does not change whether it is grown on InP or silicon. The question isn't whether it functions (it clearly does), but whether performance, defect density, dark current, and reliability meet target specs while achieving manufacturable yields on 200–300mm silicon."
So lets remove the substrate out of the equation. How does Aeluma create an equal or better InGaAs SWIR sensor than all the other big companies also making InGaAs SWIR sensors?
Hi Kat,
Thank you for the thoughtful question — it cuts straight to the heart of the issue.
You’re correct: InGaAs is InGaAs. The fundamental SWIR absorption physics do not change whether it’s grown on InP or silicon. Established InGaAs-on-InP suppliers have excellent devices today with strong QE, low dark current, and long qualification history.
The differentiation is not material physics — it is manufacturing architecture.
Traditional InP wafers are small-diameter (often 2–4 inches), higher-cost substrates that limit die count per wafer and constrain scaling into cost-sensitive, high-volume markets.
Aeluma’s approach integrates InGaAs onto large-diameter (200–300mm) silicon wafers using CMOS-aligned processing. The implications are structural:
• materially higher die count per wafer
• potential for significantly lower cost per unit at scale
• better alignment with automated silicon manufacturing flows
• tighter integration with CMOS electronics and photonics
Publicly disclosed data suggests competitive QE and dark current metrics within targeted regimes, including elevated-temperature testing relevant to automotive and defense environments. The remaining proof point is sustained yield, reliability, and qualification at wafer scale.
So the comparison is not “InGaAs vs InGaAs.”
It is “InGaAs on small InP wafers” versus “InGaAs on large silicon wafers integrated into silicon infrastructure.”
If Aeluma can maintain performance while achieving silicon-scale economics, differentiation emerges at the cost and integration level — not the raw material level.
That is the crux of the moat question — and why execution at scale could create meaningful economic differentiation.
Happy to discuss specific competitors or qualification timelines further if helpful.